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Part 1
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Basics
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Pages
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10/22/2019
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Introduction; digital abstraction; information, coding (fixed/variable length); number representation; Hamming distance
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1-32
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10/29/2019
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Boolean algebra; Huntington's axioms; DeMorgan's laws; propositional logic; switching algebra; function representations
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33-60
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Nov. 05, 2019
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Switching functions; minterm/Maxterm representations; main theorem of switching algebra; canonical forms; KV diagrams; basic systems
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61-83
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Nov. 12, 2019
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Evolution theorem; assignments; don't care; simplification: summarize (ax. V, block), transform, transformation table, KV minimization; term (order); (complete) covering; definitions: (essential) prime term, implicant, etc.
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84-115
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Part 2
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Switching networks
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Nov 19, 2019
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KV minimization; switching networks, combinat. Contract; design flow; example: 2x2 bit multiplier; Quine/McCluskey minimization: quine tables, coverage function, bundle minimization
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116-146
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11/26/2019
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Pos./neg. logic; output/input tolerance; MOS-FETs, gates, inverters, pullup/pulldown networks; NAND, NOR, AND; propagation delay, hazards: stat. 0-/1-hazard, full coverage, dyn. hazards
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147-175
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11/26/2019 Evening
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Wrapup Fundamentals: 6:00 pm to 8:00 pm, HS 0425: table -> formula -> KV ->table; circuit diagram; KV minimization.
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Part 3
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Switchgear
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Dec. 03, 2019
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Switching circuits: feedback, output and transition behavior; representation (also blackboard); Moore/Mealy distinction; description: table, state transition graph; example (synch. memory element); taxonomy; master-slave flip-flop
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176-200
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Dec. 10, 2019
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Analysis of RS flip-flop, clocking, clocked RS flip-flop, clocked D flip-flop
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201-226
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12/17/2019
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Timed MS-FF, state-specific functions, transition diagram; JK-FF, D-FF: characteristic equation; switch synthesis: sequence, state encoding, driving equations for FFs
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227-250
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12/17/2019 Evening
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Wrapup Switching Networks: 6:00 pm to 8:00 pm, HS 0425: KV&KV minimization; formula->circuit diagram; KValgebr. minimization; automaton design: task->transition diagram->transition table->KVmin.->equation->circuit (example: holding element); hazards.
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Vacations
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Christmas break
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14.01.2020
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FF control: tabular Verf., case discrimination, coefficient comparison (example: counter); design example: series adder
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251-272
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21.01.2020
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Zeitverhalten: Gate delay, critical path, FFs: setup, hold, and clock-to-Q times; clock period construction; path optimization; data ready time; counter/counter design; registers: construction, shift register, left/right shift, register file
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273-303
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Part 4
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Complex circuits
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28.01.2020
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Binary addition; two's complement; full adder, half adder, RCA: ripple carry adder; multiplication: special cases, basic structure of base cell, tiling structure
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304-329
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04.02.2020
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MSI-Schaltungen: Decoder, decoder switching networks (ex. comparator), demultiplexer, multiplexer, multiplexer switching networks/MUX for function realization (3 and more variables), read memory/ROM; Programmable logic: PLA, PAL
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330-366
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02/04/2020 Evening
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Wrapup Switching Networks: 6:00 p.m. to 8:00 p.m., HS 0425 (Topics: your questions; modulo counters if applicable, wdh. registers, codes, arithmetic).
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11.02.2020
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Microprogram control unit (see additional slides); MUX as function table, LUT, FPGA (CLB, switch matrix, array structure)
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367-382
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Feb. 11, 2020 evening
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Wrapup design, etc.: 6:00 p.m. to 8:00 p.m., HS 0425: full adder (algebraic); MUX, demux, decoder
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