Dr. Nicolai Fiege

I am sitting in room 0339 (entrance via room 0335).

• 2021–2026: Ph.D., Dr.-Ing., Electrical Engineering (Dissertation: “High-Level Synthesis Algorithms for Optimal Microarchitecture Generation”)
• Since 2021: Research Employee, University of Kassel
• 2018–2021: Master’s in Electrical Engineering, University of Kassel (Thesis: “Throughput-Optimal Modulo Scheduling with Rational Initiation Intervals for Computer-Aided Hardware Design,” VDE Award for Outstanding Academic Achievement)
• 2014–2018: Bachelor’s Degree in Electrical Engineering, University of Kassel (Thesis: “Automatic VHDL Code Generation of Convolutional Neural Networks for System-on-Chips”)

• N. Fiege, “High-Level Synthesis Algorithms for Optimal Microarchitecture Generation,” Ph.D. dissertation, University of Kassel, 2026. doi: 10.17170/kobra-2026060212196.
• N. Fiege and P. Zipf, “Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 45, no. 5, pp. 2307–2320, May 2026, doi: 10.1109/TCAD.2025.3612335.
• N. Fiege and P. Zipf, “Improving Boolean Satisfiability-Based Modulo Scheduling,” in the 35th International Conference on Field-Programmable Logic and Applications (FPL), September 2025, pp. 204–212. doi: 10.1109/FPL68686.2025.00037.
• N. Fiege, M. Hardieck, and P. Zipf, “Multiplexer Optimizations for Virtex FPGAs,” in 2025 35th International Conference on Field-Programmable Logic and Applications (FPL), Sep. 2025, pp. 55–59. doi: 10.1109/FPL68686.2025.00019.
• N. Fiege and P. Zipf, “Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design,” ACM Trans. Reconfigurable Technology and Systems, vol. 18, no. 1, p. 12:1–12:36, Jan. 2025, doi: 10.1145/3705325.
• N. Fiege, M. Kumm, and P. Zipf, “Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 1, pp. 249–261, Jan. 2024, doi: 10.1109/TCSI.2023.3327814.
• N. Fiege and P. Zipf, “BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining,” ACM Trans. Reconfigurable Technology and Systems, vol. 16, no. 3, p. 49:1–49:32, July 2023, doi: 10.1145/3599972.
• N. Fiege, P. Sittel, and P. Zipf, “Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis,” in 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2022, pp. 262–269. doi: 10.1109/FPL57034.2022.00047.
• N. Fiege, P. Sittel, and P. Zipf, “Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals,” in 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2022, pp. 322–326. doi: 10.1109/FPL57034.2022.00056.
• N. Fiege, P. Sittel, and P. Zipf, “Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling,” in 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2022, pp. 1–2. doi: 10.1109/FCCM53951.2022.9786117.
• P. Sittel, N. Fiege, J. Wickerson, and P. Zipf, “Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 614–627, Mar. 2022, doi: 10.1109/TCAD.2021.3060320.
• P. Sittel, N. Fiege, M. Kumm, and P. Zipf, “Isomorphic Subgraph-based Problem Reduction for Resource-Minimal Modulo Scheduling,” in 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Dec. 2019, pp. 1–8. doi: 10.1109/ReConFig48160.2019.8994768

I am interested in various topics of circuit optimization (especially high-level synthesis & arithmetic) but also in general optimization "no matter what". Topics for open papers can be found in the slide set with available topics in the Moodle course "Seminar and Project in Digital Technology" of the current semester.

Almost all of the listed papers can be completed both as a project and as a thesis. If you are interested or have questions about individual topics, please contact me by e-mail. Alternatively, you are also welcome to submit your own (thematically suitable) topic suggestions.

In any case, please write in your e-mail 1) what type of work you are looking for (project, seminar or thesis), 2) what topic you are interested in, 3) what previous knowledge you have and 4) what you are studying.

• Julian Werner "Arithmetic Operator Library, including C++ API & Port of Origami-HLS to Python" (Project)
• Christoph Becker "Optimal Circuit Synthesis for NAND Gates" (Project)
• Maximilian Siebald “Adder Optimization with SAT Solvers” (Project)
• Paul Girshausen “SAT Solver Library” (Project)
• Alaa Al Fares and Claudius Ertmer “Creation of Instructional Videos for Digital Logic Using Manim” (Student Assistant)

2026

• Lina Roeser “Factorization with SAT Solvers” (Project)
• Oliver Preuß and Alexander Rebbe “Design and Commissioning of a 3D-Printed Robotic Arm” (Project)

2025

• Florian Zimmermann “Design and Implementation of an FPGA-Based GPU with RISC-V Cores” (Bachelor’s thesis)
• Jan Philipp Rauwolf “FPGA-Accelerated Vibration Localization” (Bachelor’s)

2024

• Achmad Luthfi Nugroho "Optimal Matrix Multiplication Using Integer Linear Programming" (Project)
• Achmad Luthfi Nugroho "Implementation of a Method for Optimized FIR Filter Implementation" (Bachelor's)
• Guanyu Qiu "Accelerating Boolean Satisfiability Solvers on FPGAs" (Master's)
• Florian Zimmermann, “FPGA-Accelerated Rendering of 3D Scenes” (Project)
• Philipp Schenk, "Non-Iterative Modulo Scheduling" (Bachelor's)
• Michel Schäfer and Timo Busch, "Metrological Analysis of the Coffee Roasting Wheel" (Project)
• Christoph Becker, “Optimal Constant-Matrix Multiplication Using Boolean Satisfiability” (Bachelor’s)

2023

• Philipp Schenk, "Generic C++ API for Boolean Satisfiability Solvers" (Project)
• Jan Philipp Rauwolf, "Triangulation of Vibrations" (Project)
• Lucas Scheerer "How SAT Solver Algorithms Work" (Project)
• Christoph Becker "Heuristic Modulo Scheduling with Rational IIs" (Project)
• Benjamin Lagershausen-Keßler "SMT-Based Modulo Scheduling" (Bachelor's)

2022

• Benjamin Lagershausen-Keßler "Implementation of the Ethernet Interface on the PYNQ Board" (Project)
• Guanyu Qiu "Design and Implementation of a Signal Generator" (Project)

Summer Semester 2026

• VHDL Course/Circuit Design with HDLs

Winter Semester 2025/26

• Optimization and Verification of Digital Circuits (new!)

Summer Semester 2025

• VHDL Course/Circuit Design with HDLs

Winter Semester 2024/25

• VHDL Lab

Summer Semester 2024

• VHDL Course/Circuit Design with HDLs

Winter Semester 2023/24

• Digital Logic Lab
• VHDL Lab (canceled due to lack of participants)

Summer Semester 2023

• VHDL Course/Circuit Design with HDLs

Winter Semester 2022/23

• Digital Logic Lab
• VHDL Lab
• Embedded Systems Lab

Summer Semester 2022

• VHDL Course/Circuit Design with HDLs

Winter Semester 2021/22

• Digital Logic Lab
• VHDL Lab

Summer Semester 2021

• VHDL Course/Circuit Design with HDLs

We are often asked for "instructions" for project and final papers. Here is a small collection of information on how to write a good thesis:

• You can find general tips on the structure of written theses on the Computer Science course page: https: //www.uni-kassel.de/eecs/studium/bachelor/informatik#c1006263 (PDF "Ratgeber Abschlussarbeit" by Prof. Wegner)
• Andrey Churkin has a nice video on how to produce sensible illustrations: https: //www.youtube.com/watch?v=i-HAjex6VtM (the video refers to scientific publications, but the information can be applied just as well to student papers!)
• LaTeX templates from our department are available on request by e-mail (please do not use Word...!)