VHDL course and internship

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This course is aimed at Bachelor students (2V+2Ü, 6 CP). As a Master (Computer Science), please register for the course "Schaltungsentwurf mit HDLs" (2V+2Ü, 6 CP)

General information

The VHDL course and the VHDL practical course are two thematically related but independent courses that deal with the design and synthesis of modern digital circuits using a hardware description language (VHDL).

These courses are offered in complementary alternation with courses in the subject area "Computer Architecture and System Programming", so that both courses are held each semester. The course offered in the summer semester corresponds to the course "Selected Chapters of Computer Architecture" (course no. FB16-6804); the practical course in the winter semester corresponds to the course "Selected Chapters of Computer Technology and Microprocessor Technology" (course no. FB16-yyyy).

Please note that our courses can only be credited if you have not yet completed Prof. Börcsök's courses.

Contents and goals

The course is primarily aimed at computer scientists, electrical engineers and mechatronics engineers with a focus on "computer engineering" or with an interest in modern design processes in microelectronics.

VHDL course

In the VHDL course, the hardware description language VHDL is learned in a combination of lecture and computer exercises and the developed designs are synthesized on an FPGA board. Contents of the course include syntax and semantics of VHDL, various modeling options, description of standard functionalities (switching networks, state machines, data path functionality) as well as synthesis of concrete circuits with commercial CAD software.

VHDL internship

In the VHDL practical course, the skills acquired are deepened and consolidated within a somewhat larger hardware design project. Based on the modelling of a processor model with pipelining, system modelling in VHDL, simulation and validation of the models created, synthesis on a standard cell library, characterization of the implementation and testing of the models on a prototype hardware will be part of the practical course.

Materials

Extensive materials are provided in Moodle for both the course and the practical course. Please be sure to register for your respective Moodle course.

All course materials and a discussion forum can be found in the Moodle course of the respective course. Please be sure to register for this in Moodle.

Times

The VHDL course takes place every summer semester on Wednesdays between 10:00 and 13:00 in room WA -1201 (CIP pool).

The VHDL practical course takes place every winter semester on Mondays between 10:00 and 13:00 in room WA 0334 (seminar room of the FG).

In the case of the practical course, this time is to be understood as "supervised pool time".

Literature

  • Volnei A. Pedroni: Circuit Design And Simulation With VHDL; With Press Ltd, Second Edition, (November 2, 2010). ISBN: 0262014335

In addition, the following books are relevant to the lecture content:

 

  • Jürgen Reichardt, Bernd Schwarz: VHDL-Synthese: Entwurf digitaler Schaltungen und Systeme, Oldenbourg; Auflage: 5., aktualisierte Auflage. (July 29, 2009), ISBN: 3486589873
  • Frank Kesel, Ruben Bartholomä: Entwurf von digitalen Schaltungen und Systemen mit HDLs und FPGAs: Einführung mit VHDL und SystemC, Oldenbourg; Edition: 2nd, corrected edition. (January 28, 2009), ISBN: 3486589768
  • Peter Ashenden: The Designer's Guide to VHDL, Morgan Kaufmann; Edition: 3rd revised edition. (November 11, 2006), ISBN: 0120887851
  • Paul Molitor, Jörg Ritter:VHDL: An Introduction, Pearson Studium (April 27, 2004), ISBN: 3827370477

Proof of performance

Proof of performance in both courses is provided by a combination of an oral examination and the submission of a term paper (report, source code created). The exact modalities will be announced in the respective course.