1oo2 safety architecture with 32-bit processor

The content on this page was translated automatically.

The system consists of two subsystems, 1oo2 Safety system and 1oo1 Com system

Safety system

  • 2 x 32 bit IP cores
  • 2 power domains
  • Hardware comparator
  • Peripherals
    • Counter
    • PWM
    • 2 x SPI
    • E / A (64 inputs, 64 outputs)
  • 8 MiB SDRAM (ECC), 4 MiB Flash
  • Access to Com. system memory and peripherals

Com system

  • 1x 32 bit IP core
  • Peripherals
    • 4 x UART (2 KiB Rx/Tx FIFO)
    • 2 x CAN
    • 2 x SPI
    • I2C
    • GPIO (16 In- /Outputs)
    • 2 x Fast Ethernet
  • 8 MiB SDRAM (ECC), 4 MiB Flash