RISC-V
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system | - RISC-V 32-bit CPU - 20 Multifunctional IO with real-time IO diagnostics in hardware - On-chip Instr. RAM (16 kB) as program memory - External SPI Flash for loading the program into Instr. RAM - On-chip SRAM (4 kB) - SPI, I²C, UART for communication |
architecture | - Safe-System 1oo2D architecture with hardware comparator - Complete physical separation of both systems - Real-time IO diagnostics in hardware massively reduces software diagnostics effort and enables the fastest possible response in the event of failure |
High Performance System | - RISC-V 64-Bit High Performance CPU (optional multicore) - On-chip instruction and data cache - On-chip SRAM - MMU for operating system (e.g. Linux) - Controller for external flash connection - Controller for external DDR-RAM connection - Gigabit Ethernet - Standard peripherals |
Checker Core System | - RISC-V 32-bit CPU optimized for low energy consumption - On-Chip Flash - On-chip SRAM - Standard peripherals |
architecture | - 1oo2D architecture with flexible software comparator - Complete physical separation of both systems - Diverse hardware due to different core implementations |