1oo4 safety architecture with 32-bit processor

Design description

• Processor memory bus interfaces (PLBs) and IP cores are used for data and instruction transfer.
• Fast Simplex Link Interfaces (FSL buses) are used to interconnect the four processors.
• Output and test results via UART and GPIO modules.
• PLB_to_PLB bridges are used to provide the data and address signals from the UART and GPIO modules via PLBs.
• The MUTEX IP core is used to synchronize the process.

Design description

• 1oo4 SoC according to IEC 61508 up to SIL 3.
• Four LEON3 soft processors.
• Each processor has its own AHB bus system and on-chip RAM.
• A comparator is used to compare the CPUs and memory of the four processors.
• A MUTEX IP core is used to select which processor can be connected to the peripherals.
• If one processor fails, the system is downgraded to 1oo3.
• If two processors fail, the system is demoted to 1oo2.