RISC-V

System

-      RISC-V 32-bit CPU

-      20 Multifunctional IO with real-time IO diagnostics in hardware

-      On-Chip Instr. RAM (16 kB) as program memory

-      External SPI Flash for loading the program into Instr. RAM

-      On-Chip SRAM (4 kB)

-      SPI, I²C, UART for communication

Architecture

-      Safe-System 1oo2D architecture with hardware comparator

-      Complete physical separation of both systems

-      Real-time IO diagnostics in hardware massively reduces software diagnostics effort and enables fastest possible reaction in case of failure

High Performance System

-      RISC-V 64-bit High Performance CPU (optional multicore)

-      On-Chip Instruction and Data Cache

-      On-chip SRAM

-      MMU for operating system (e.g. Linux)

-      Controller for external flash connection

-      Controller for external DDR RAM connection

-      Gigabit Ethernet

-      Standard peripherals

Checker Core System

-      RISC-V 32-bit CPU optimized for low power consumption

-      On-Chip Flash

-      On-chip SRAM

-      Standard peripheral

Architecture

-      1oo2D architecture with flexible software comparator

-      Complete physical separation of both systems

-      Diverse hardware through different core implementations