E-learning with tablet computers and smartphones

Short info: We are investigating how to support students and teachers in the daily routine of lectures, exercises and learning and how to provide concrete help for learning. To this end, we are developing a client-server system with apps as clients. The implementation takes place under iOS.

Student work: You will develop iOS (iPad, iPhone) apps and the connection to a server software. If you are interested, we also support work with Android. Just get in touch with us to clarify the details!

Brief info: We are working on FPGA circuits for beam control for a particle accelerator near Darmstadt. These circuits have to fulfill extreme time constraints (in the nanosecond range).

Student work: Interesting for electrical engineers and computer scientists! You develop FPGA circuits (Bachelor's/Master's theses) with FPGAs at the limits of what is feasible. Just get in touch if you are interested!

More information about the project: here

The e-learning software to be developed as part of the project(for iPad, iPhone and Android) aims to support students and teachers in the daily routine of lectures, exercises and learning. In addition, however, the student-side software should be used in such a way that specific support and encouragement (advising) of individual students is achieved, also in connection with small learning groups that find themselves.

The possibilities of modern tablet computers and smartphones should be used to provide computer-based teaching and learning support. The main aim is to directly accompany lecture-based teaching, associated exercises and supplementary materials by providing interaction within lectures and immediate feedback of the data. Together with a subsequent analysis, student deficits can be recognized and problem areas within individual courses can be identified. Based on this, long-term improvements can then be made to the teaching material, while short-term remedies such as additional tutorials or simply repetition of material can also be offered. The necessary data is available directly after each course and in some cases during the course itself.

Students are also offered highly individualized learning advice and progress analysis based on all available data. Through interaction between the end devices assigned to the individual students, contacts for and between learning groups can also be suggested and supported.

The aim of the project is therefore to provide a corresponding software environment for lecturers and students and to adapt it optimally to the "lecture" field of application. One of the main aspects here is that the tried-and-tested way of holding such events does not have to be radically changed, but that the additional options can be integrated as required in a complementary manner and in small steps. Other event types such as seminars can already be investigated during the project to determine which software enhancements would be necessary to support them. The project will be accompanied didactically in cooperation with the SCL and the concept pursued will be continuously improved on the basis of this advice and interim results.

Highly specialized systems are required for resource-critical applications in order to achieve the required performance and energy efficiency at the same time. Single-chip systems, so-called system-on-chips (SoC), are an implementation option. Reconfigurable circuits (the best known representatives of which are FPGAs) not only offer the possibility of implementing such systems without designing and manufacturing a further specialized VLSI chip (ASIC) due to their now sufficiently large gate capacity, but also allow a dynamic change of the implemented functionality during operation. This means that the structure of the hardware can be temporarily adapted to requirements, which can increase both performance and energy efficiency. Such systems are called System-on-Programmable-Chip (SoPC).

The ability to reconfigure comes at the cost of additional hardware, which initially entails disadvantages in terms of space, performance and energy efficiency. However, these can be partially compensated for by a clever application of dynamic partial reconfiguration (exchange of partial functionality at runtime). The implementation of the reconfiguration process is particularly critical.

Our research deals with the possibilities of this compensation. Both FPGA-based implementations and newly designed reconfiguration structures are examined and compared. Among other things, we are concerned with the question of whether dynamic reconfiguration must use the programmability of the underlying hardware in order to be efficient, or whether meta-reconfiguration is sufficient, i.e. whether it can be abstracted from the hardware. Our applications are in the area of real-time data processing in embedded hardware systems. To this end, we have been working on wireless sensor network nodes for some time and are currently also starting to develop camera data processing. In future, the processing of flight status data will also be added as part of the UniKOPTER project. In all cases, attempts are being made to achieve better system properties through hardware implementations of the required algorithms.

Theses are available for students in this research area (Bachelor, Master, D1/D2). Previous knowledge of digital circuit design, hardware description languages (VHDL or Verilog) or microprocessor systems is advantageous.

FAIR is a new, international accelerator facility for research with antiprotons and ions, which is to be built in the next few years by the GSI (Gesellschaft für Schwerionenforschung) near Darmstadt (click here for the FAIR website of the GSI).As part of the FAIR project, barrier bucket systems for flexible particle beam manipulation are planned, for which control electronics, a barrier bucket low-lever radio frequency system (BB-LLRF), are required.

Our project in collaboration with GSI is focused on the realization of this BB-LLRF system. Our developments should be suitable for implementation on an FPGA platform. In addition, the real-time data supply associated with the BB-LLRF system and the connection to the control system will be addressed. FPGA-based subsystems are already used extensively in the area of RF systems in the SIS100 and for the FAIR project, so that previous experience can be drawn on for this. What is new in the context of this project is the time resolution below 1 ns. This must be achieved within the FPGA, which requires special investigations and designs. In this context, possibilities for continuous signal phase alignment based on an external reference will probably also have to be investigated. The main objectives of the planned work are

• the selection of a suitable signal synthesis method for the barrier pulses,
• the implementation of the synthesis method on a GSI FPGA system,
• the investigation and realization of a calibration and adjustment procedure for the precision timing of the signal synthesis,
• the development of an interface to the control system and the optical trigger distribution for the ring-to-ring transfer.

The project thus includes all components and implementations that are necessary for a prototypical realization and system integration of the BB-LLRF system. Accordingly, a prototype installed at GSI will be set up during the project period in cooperation with GSI, on which the functionality of the individual results can be tested in experimental operation and which will enable a complete demonstration of the project results at the end.

For our students: As part of this project, you can work on FPGA-based circuit designs or carry out investigations on given circuits.