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Part 1
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Basics
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Pages
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22.10.2019
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Introduction; digital abstraction; information, coding (fixed/variable length); number representation; Hamming distance
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1-32
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29.10.2019
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Boolean algebra; Huntington's axioms; DeMorgan's laws; propositional logic; switching algebra; function representations
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33-60
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05.11.2019
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Switching functions; minterm/maxterm representation; main theorem of switching algebra; canonical forms; KV diagrams; basic systems
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61-83
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12.11.2019
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Development theorem; assignments; don't care; simplification: summarize (ax. V, block), transform, transformation table, KV minimization; term (order); (complete) covering; definitions: (essential) prime term, implicant etc.
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84-115
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Part 2
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Switching networks
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19.11.2019
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KV minimization; switching networks, combinat. Contract; design flow; example: 2x2 bit multiplier; minimization according to Quine/McCluskey: Quine tables, covering function, bundle minimization
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116-146
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26.11.2019
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Pos./neg. logic; output/input tolerance; MOS-FETs, gates, inverters, pull-up/pull-down networks; NAND, NOR, AND; propagation delay, hazards: stat. 0-/1-hazard, complete coverage, dyn. hazards
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147-175
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26.11.2019 Evening
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Wrapup Basics: 18:00 to 20:00, HS 0425: Table -> Formula -> KV ->Table; Circuit diagram; KV minimization
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Part 3
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Switchgear
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03.12.2019
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Switchgear: feedback, output and transition behavior; representation (also blackboard); Moore/Mealy distinction; description: table, state transition graph; example (synch. memory element); taxonomy; master-slave flip-flop
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176-200
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10.12.2019
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Analysis of the RS-FlipFlop, clocking, clocked RS-FlipFlop, clocked D-FlipFlop
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201-226
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17.12.2019
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Synchronized MS-FF, state-specific functions, transition diagram; JK-FF, D-FF: characteristic equation; switch synthesis: sequence, state coding, control equations for FFs
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227-250
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17.12.2019 Evening
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Wrapup switching networks: 18:00 to 20:00, HS 0425: KV&KV minimization; formula->circuit diagram; KValgebr. minimization; automaton design: task->transition diagram->transition table->KV-Min.->equation->circuit (example: holding element); hazards
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Vacation
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Christmas break
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14.01.2020
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FF-Control: Tabular Verf., case differentiation, coefficient comparison (example: counter); design example: series adder
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251-272
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21.01.2020
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Zeitverhalten: Gate delay, critical path, FFs: setup, hold and clock-to-Q times; structure of a clock period; path optimization; data ready time; counter/counter design; registers: structure, shift register, left/right shift, register file
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273-303
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Part 4
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Complex circuits
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28.01.2020
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Binary addition; two's complement; full adder, half adder, RCA: ripple carry adder; multiplication: special cases, basic structure of the basic cell, tile structure
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304-329
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04.02.2020
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MSI-Schaltungen: Decoder, decoder switching networks (Ex. comparator), demultiplexer, multiplexer, multiplexer switching networks/MUX for function realization (3 and more variables), read memory/ROM; Programmable logic: PLA, PAL
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330-366
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04.02.2020 Evening
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Wrapup Schaltwerke: 18:00 to 20:00, HS 0425 (topics: your questions; modulo counters, if applicable, registers, codes, arithmetic)
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11.02.2020
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Microprogram control unit (see additional slides); MUX as function table, LUT, FPGA (CLB, switch matrix, array structure)
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367-382
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11.02.2020 Evening
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Wrapup design etc.: 18:00 to 20:00, HS 0425: Full adder (algebraic); MUX, demux, decoder
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