Digital Systems
The content on this page was translated automatically.
The course takes place in the winter and summer semester.
Dates: always on Mondays and Fridays between 10:15 and 11:45 a.m. in WA -1606
Structure: 6 CP, 3V+1Ü, 4 SWS
The lecture is intended for students of computer science, electrical engineering and mechatronics from the 4th semester and with solid previous knowledge of digital logic and computer architecture. It deals with basic design methods for pipelining, control unit design and related structures and their optimization. Basic low-power design is covered as well as board-based design of System-on-Chips (SoC) and Network-on-Chips (NoC).
The lecture (3 SWS) contains integrated exercises (1 SWS). In the exercises, essential aspects of the lecture material are examined in more detail using sample calculations or designs. In a later semester you can additionally learn the hardware description language VHDL in the VHDL course.
Learning objectives: The learner will be able to
- calculate the timing behavior of given digital circuits,
- design simple pipeline structures,
- apply pipeline optimization methods to given circuits,
- describe and apply retiming methods,
- represent and explain the structure of state machines,
- design complex state machines,
- develop optimized versions of given state machines,
- qualitatively analyze and compare implementation variants.
Materials
An extensive collection of materials will be provided for the lecture.
Literature: The following textbooks will be used in the lecture.
- Mano, M. Morris and Ciletti, Michael D.: Digital Design; Pearson International Edition; 4th ed.; 2007; ISBN 0132340437
- Katz, Randy H.: Contemporary Logic Design; Addison-Wesley-Longman; 2nd ed.; 2004; ISBN 978-0201308470
- John F. Wakerly, Digital Design: Principles and Practices Package, Addison Wesley Pub Co Inc; edition: 0004 (12 January 2006), ISBN: 0131733494
The software used can be found here:
- Icarus Verilog: iverilog.icarus.com/home (user guide: http://iverilog.wikia.com/wiki/User_Guide )
- gtkwave: http: //gtkwave.sourceforge.net/
More:
- VeriWell: http://veriwell.sourceforge.net/ - another Verilog simulator (haven't tried it yet).
- Verilog reference: https://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf
Proof of performance
Depending on the number of participants, the certificate of achievement will take the form of an oral or written examination. The exact modalities will be announced in the course.